1. Field of the Invention
The present invention relates to a phase synchronization circuit and a method thereof. More particularly, the present invention relates to a multi-channel receiver, digital edge tuning circuit and method thereof.
2. Description of Related Art
Transmission of digital signals, for example, over a digital bus using TTL or RS-232 levels or over a communications link such as a radio frequency channel or an optical fiber is well known in the art. In order to recover received data accurately, it is important to know the clock frequency of the transmitted data. This can be accomplished, for example, by using a highly stable crystal controlled clock of known frequency in the transmitter, and a similar highly accurate crystal controlled clock of the same frequency in the receiver. In this event, the frequencies are equal, although the phase of the received data stream with respect to the receiver clock cannot be guaranteed because the transmitter clock and the receiver clock are not phase controlled.
A typical structure for ensuring phase synchronization of the received data signal to the receiver clock includes a phase lock loop. A training sequence consisting of a number of non-data pulses is necessary for the phase lock loop to achieve phase lock. This overhead reduces the effective bit rate of the communication channel. Furthermore, the phase lock loop requires a large loop gain stabilization capacitor which typically cannot be formed on an integrated circuit device. The phase lock loop also requires a fair amount of circuitry, much of which is analog so that it is difficult to achieve a phase lock loop having the necessary precision and stability. It is even more difficult for such analog circuitry to be implemented in CMOS integrated circuits which are desirable for very low power consumption.
Other prior art techniques to quickly provide phase synchronization with an incoming signal is to use a very high frequency clock. However, this has severe drawbacks in being expensive and difficult to maintain a reliable very high frequency clock.